1. Technical Field of the Invention
The present invention relates to devices which include volatile memory cells and, more particularly, to circuitry for responding to a tamper detection situation by clearing stored data within those volatile memory cells.
2. Description of Related Art
A commonly used structure for a volatile memory cell comprises the well known 6T memory cell. A conventional 6T memory cell structure is shown in FIG. 1. The 6T cell comprises a four transistors 10, 12, 14 and 16 arranged in a cross-coupled latch 18 configuration with two access transistors (pass gates) 20 and 22 connected thereto for allowing bit line (BL and BLC) access to the latched complementary logic values (at nodes T and C) stored by the latch.
Volatile memory cells are utilized in a number of different applications to store data. It is not uncommon for such memory cells to be used in secure applications such as in a smart card (see, FIG. 2) in order to store user and account related data. It is critically important to protect the security of that stored data. To that end, a need exists in the art to destroy the stored data in response to detection of a tamper situation (such as, for example, when an unauthorized individual attempts to access the memory cells).